1. Technical Field
The present invention relates to simulation and testing methodology, more specifically to apparatus and methods for designing simulation models for use in designing and testing complex devices, such as network switch devices.
2. Background Art
Switched local area networks use a network switch for supplying data frames between network stations, where each network station is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) enabling a network interface within each network node (including the switch) to access the media.
An important consideration in the design and implementation of complex device structures, such as a network switch implemented on an integrated circuit, involves the methodology used for designing and testing the complex device structure. Specifically, the functionality of a complex device is often enhanced with test structures or stored test routines in order to determine whether the manufactured device will work for its intended purpose. Although designing a device testability is not strictly an essential component for device operability, early design and implementation of device testability provides more efficient resources for debugging device prototypes, identifying and locating manufacturing defects in the device, as well as identifying failures that may occur in the device over time due to other hardware or software.
Different computer aided design and simulation systems have been developed to assist circuit designers in simulating circuit design and performance prior to reduction to silicon. For example, a design tool known as the Mentor Fastscan, manufactured by Mentor Graphics, Inc., has a modeling technique where enabling simulation of basic circuit components, for example, a basic random access memory (RAM). Although the Mentor Fastscan tool is capable of modeling a block of custom logic or a RAM or a ROM, the above-described system is unable to model more complex structures, where a device may have state-dependent units implemented on the device. For example, a logic array composed of logic arrays and memory components having multiple states may need to be modeled by counting the number of memory elements (e.g., flip-flops). Accurate modeling of such a complex logic array may require generating a permutation of models corresponding to an exponential number (2 .sup.N) of the memory elements, where N equals the number of memory elements. Alternatively, the array may be modeled by the modeling tools as a black box, where the internal structure of the array is not known to the tool. In this case, any logic driving the array or driven by the array would be untestable, since faults in the logic driving the array would be unobservable, and faults in the logic driven by the array would be uncontrollable.